Development of Library Components for Floating Point Processor

Author & Affiliation:
SUBHASH KUMAR SHARMA
Department of Electronics, M.G.P.G. College, Gorakhpur (India)
SHRI PRAKASH DUBEY
Department of Physics , M.G.P.G. College, Gorakhpur (India)
ANIL KUMAR MISHRA
Department of Physics , M.G.P.G. College, Gorakhpur (India)
Keyword:
Binary, Decimal conversion, Floating point representation, Simulations and Device Utilization
Issue Date:
April 2021
Abstract:

This paper deals with development of an n-bit binary to decimal conversion, decimal to n bit binary conversion and decimal to IEEE-754 conversion for floating point arithmetic logic unit (FPALU) using VHDL. Normally most of the industries now a days are using either 4-bit conversion of ALU or 8-bit conversions of ALU, so we have generalized this, thus we need not to worry about the bit size of conversion of ALU. It has solved all the problems of 4-bit, 8-bit, 16-bit conversions of ALU’s and so on. Hence, we have utilized VHSIC Hardware Description Language and Xilinx in accomplishing this task of development of conversions processes of ALU

Pages:
42-50
ISSN:
2319-8044 (Online) - 2231-346X (Print)
Source:
DOI:
http://dx.doi.org/10.22147/jusps-A/330402
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Copy the following to cite this article:

S. K. Sharma; S. P. Dubey; A. K. Mishra, "Development of Library Components for Floating Point Processor", Journal of Ultra Scientist of Physical Sciences, Volume 33, Issue 4, Page Number 42-50, 2021

Copy the following to cite this URL:

S. K. Sharma; S. P. Dubey; A. K. Mishra, "Development of Library Components for Floating Point Processor", Journal of Ultra Scientist of Physical Sciences, Volume 33, Issue 4, Page Number 42-50, 2021

Available from: https://www.ultrascientist.org/paper/1544/

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