In this paper a layout design of an ultra-compact CMOS inverter using silicon nanowire field effect transistor with minimal power dissipation while matching the transient performance of bulk and SOI CMOS circuits is proposed. In this study, we took into account the strengths of nanotechnology including low static and dynamic power dissipation, suppression of short channel effect (SCE) and drain-to-source breakdown voltage, surface mobility enhancement and the ease of manufacturability. We analyzed different component which gives low static power dissipation. Once the body dimensions are determined, dc characteristics of the optimal n and p-channel transistors are evaluated in terms of SCE, DIBL, drain-to-source breakdown voltage and noise margin (NM). In this paper layout extraction is presented, which is a method of achieving low dynamic power dissipation.